1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device and a control method thereof, and more specifically, to a technology of controlling read/write operations of a nonvolatile ferroelectric memory cell by embodying a memory cell whose channel resistance changes according to a polarity state of a ferroelectric material making up the cell array in a nano scale memory device.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and preserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes a high residual polarization characteristic of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents over the above FeRAM are disclosed in the U.S. Pat. No. 6,775,172 by the same inventor of the present invention. Therefore, the basic structure and the operation over the FeRAM are not described herein.
A unit cell of a nonvolatile FeRAM device includes a switching unit and a nonvolatile ferroelectric capacitor. The switching unit performs a switching operation depending on a state of a word line to connect a nonvolatile ferroelectric capacitor to a sub bit line. The nonvolatile ferroelectric capacitor is connected between a plate line and one terminal of the switching unit. Here, the switching unit of the FeRAM is a NMOS transistor whose switching operation is controlled by a gate control signal.
However, in the nonvolatile FeRAM device, as a cell size becomes smaller, the data retaining characteristic of the device is degraded. Consequently, proper operation of the cell becomes increasingly difficult. That is to say, as voltage is applied to an adjacent cell in a read mode of the cell, data is destroyed to generate an interface noise between cells. Additionally, in a write mode of the cell, as a write voltage is applied to an unselected cell, data of unselected cells is destroyed. Consequently, random access of the memory device becomes difficult.